Menning av realtíð fleirkjarnu samskifti og synkronisering
Tórur Biskopstø Strøm
Stuðul úr Granskingargrunninum:
A multi-core architecture enables in principle a performance increase proportional to the number of cores, compared to similar single-core architecture. However, this performance benefit is typically limited by sequential code, synchronization overhead, and communication congestion. These issues become more apparent in real-time systems where the performance is limited by the worst-case execution time. This project aims to alleviate some of these issues, allowing multi-core architectures to come closer to their full performance potential.
The goal of the project is to submit three papers on the subject that aim to create or optimize technology for multicore synchronization and communication, concluded by the Ph.D. thesis. The technology developed will be of use within the real-time community and possibly in mobile phones and personal computers.
The project is structured as a 2-year Ph.D. project with 4 half-year milestones. Each main goal is represented as a milestone, one for each paper and one for the thesis. In addition to the work on the papers, compulsory course and dissemination work is planned.
Part of the dissemination work is planned to be done in cooperation with the University of the Faroe Islands, either as co-supervisor to bachelor students, teaching assistant in remote courses or actual teacher in courses converted from remote to local.
Synchronization and communication mechanisms have been investigated during this project, and based on the findings, three new hardware mechanisms have been developed. The first, the Hardlock, is a hardware locking mechanism with low lock acquisition and release overhead (2 and 1 clock cycles, respectively). The second is a pool of scratchpad memories with programmable time division multiplexing schedules to improve communication between cores. The third is a hardware transactional memory unit to reduce the synchronization complexity. All three units have bounded overhead and are starvation free, making them appropriate for hard real-time systems.
PhD Thesis defended on 2nd October 2019. Title: Real-Time Synchronization on Multi-Core Processors.
Scientific articles, books, thesis etc.
Tórur Biskopstø Strøm and Martin Schoeberl. “Hardlock: a Concurrent Real-Time Multicore Locking Unit”. In: 2018 IEEE 21st International Symposium on Real-Time Distributed Computing (ISORC). IEEE. 2018, pp. 9–16.
Tórur Biskopstø Strøm, Jens Sparsø, and Martin Schoeberl. “Hardlock: Real-time multicore locking”. In: Journal of Systems Architecture (2019).
Martin Schoeberl, Tórur Biskopstø Strøm, Oktay Baris, and Jens Sparsø. “Scratchpad Memories with Ownership”. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE. 2019, pp. 1216– 1221.
Oktay Baris, Shibarchi Majumder, Tórur Biskopstø Strøm, Anders la Cour-Harbo, Jens Sparsø, Thomas Bak, and Martin Schoerbel. “Demonstration of a Time-predictable Flight Controller on a Multicore Processor”. In: Proceedings of the 22nd IEEE International Symposium on Real-time Computing (ISORC 2019). IEEE. 2019, pp. 95–96.
Storage and access rights to collected data
All the hardware is open source and available as part of the Patmos processor at: https://github.com/t-crest/patmos